$include (defines.inc)

	org		0000h
	ajmp 	start

	org		Int6_rt
	clr		IE01.0
	ajmp	spi_irq

	org		Int7_rt
	clr		IE01.1
	AJMP	spi2_irq

	org		Int8_rt
	clr		IE01.2
	ajmp	can_irq

	ORG		Int9_rt
	clr		IE01.3
	AJMP	can2_irq

	org		Program_Start_Address

spi_irq:
	MOV		SPI_SR,#00000000B	;CLR irq request
	MOV		P0,SPI_DATA
	SETB	IE01.0
	
	reti

spi2_irq:
	MOV		SPI2_SR,#00000000B
	MOV		P1,SPI2_DATA
	SETB	IE01.1

	RETI

can_irq:
  	MOV		EO,#00000000B
	MOV		A,0DCH		;clr irq request
	JZ		can_irq_end		;no interrupt, exit irq
	
	MOV		R0,A		
	ANL		A,#00000010b	;test if transmit interrupt
	JNZ		can_trans_irq
	MOV		A,R0
	ANL		A,#00000001b	;test if receive interrupt
	JNZ		can_receive_irq
	AJMP	can_irq_end

can_trans_irq:
	MOV 	P0,#0A8H
	AJMP	can_irq_end
	
can_receive_irq:
	MOV		P0,0E6H
	MOV		P1,0E7H
	MOV		P2,0E9H
	MOV		P3,0EAH

	MOV		0DAH,#00000100B	//release buffer to clr the receive irq.

	can_irq_end:
	SETB	IE01.2
	reti

can2_irq:
	MOV		EO,#10000000B 
  	MOV		A,0DCH		;clr irq request
	JZ		can2_irq_end		;no interrupt, exit irq
	
	MOV		R0,A		
	ANL		A,#00000010b	;test if transmit interrupt
	JNZ		can2_trans_irq
	MOV		A,R0
	ANL		A,#00000001b	;test if receive interrupt
	JNZ		can2_receive_irq
	AJMP	can2_irq_end

can2_trans_irq:
	MOV 	P0,#0A8H
	AJMP	can2_irq_end
	
can2_receive_irq:
	MOV		P0,0E6H
	MOV		P1,0E7H
	MOV		P2,0E9H
	MOV		P3,0EAH

	MOV		0DAH,#00000100B	//release buffer to clr the receive irq.

	can2_irq_end:
	SETB	IE01.3
	reti

start:
	setb	IE.7	;enable all interrput
;begin spi test
	setb	IE01.0	;enable xintr 6
	MOV 	SPI_PRER, #00001000B   ;write prer
	MOV		SPI_CR,#11000000B	   ;write spi enable and interrput enable
	MOV		SPI_DATA,#11001100B	   ;send 11001100B

;BEGIN SPI2 TEST
	SETB	IE01.1
	MOV		SPI2_PRER,#00011111B
	MOV		SPI2_CR,#11000000B
	MOV		SPI2_DATA,#10101100B

;begin can test
	MOV		EO,#00000000B	;choose can1 register
	setb	IE01.2	;ENABLE XINTR 8
	MOV		0DEh,#00000001B	;write timing0
	MOV		0DFh,#00101111B	;write timing1
	MOV		0F6h,#10000000B	;write clock divider register, extended mode
	MOV		0E6h,#0A6H	;write acceptance code 0 to 3 and mask 0 to 3
	MOV		0E7H,#0B0H	
	MOV		0E9H,#12H
	MOV		0EAH,#30H
	MOV		0EBH,#0FFH
	MOV		0ECH,#0FFH
	MOV 	0EDH,#0FFH
	MOV		0EEH,#0FFH

	MOV		0D9H,#00000100b	;set selftest mode and exit the reset mode
	MOV		0DDH,#0FFH	   ;enable all interrupt

	MOV		0E6h,#83H	;write tx buffer
	MOV		0E7H,#0ABH	
	MOV		0E9H,#0BCH
	MOV		0EAH,#0CDH
	MOV		0EBH,#56H
	MOV		0ECH,#0deH
	MOV 	0EDH,#0adH
	MOV		0EEH,#0beH

	LCALL	DELAY	;delay sometime 

	MOV		0DAH,#00010010B	  	;start selftransmit and don't retry

;begin can2 test
	setb	IE01.3	;ENABLE XINTR 9
	MOV		EO,#10000000B			  ;choose can2 register
	MOV		0DEh,#00000001B	;write timing0
	MOV		0DFh,#00101111B	;write timing1
	MOV		0F6h,#10000000B	;write clock divider register, extended mode
	MOV		0E6h,#0A6H	;write acceptance code 0 to 3 and mask 0 to 3
	MOV		0E7H,#0B0H	
	MOV		0E9H,#12H
	MOV		0EAH,#30H
	MOV		0EBH,#0FFH
	MOV		0ECH,#0FFH
	MOV 	0EDH,#0FFH
	MOV		0EEH,#0FFH

	MOV		0D9H,#00000100b	;set selftest mode and exit the reset mode
	MOV		0DDH,#0FFH	   ;enable all interrupt

	MOV		0E6h,#83H	;write tx buffer
	MOV		0E7H,#12H	
	MOV		0E9H,#23H
	MOV		0EAH,#34H
	MOV		0EBH,#56H
	MOV		0ECH,#0deH
	MOV 	0EDH,#0adH
	MOV		0EEH,#0beH

	LCALL	DELAY	;delay sometime 

	MOV		0DAH,#00010010B	  	;start selftransmit and don't retry

WHILE:	
	AJMP	WHILE

DELAY:
	MOV		R7,#10
D1:	MOV 	R6,#50
D2:	DJNZ 	R6,D2
	DJNZ	R7,D1
	RET

	DJNZ	R7,DELAY

END